1) Field of the Invention
The present invention relates to a clock control circuit apparatus equipped with an oscillation circuit for generating a first clock signal through the use of an oscillator and a CR oscillation circuit capable of adjusting an oscillation frequency of a second clock signal, and further to a microcomputer equipped with the clock control circuit apparatus.
In addition, the present invention relates to a microcomputer including an oscillation circuit for generating a first clock signal through the use of an oscillator and a CR oscillation circuit capable of adjusting an oscillation frequency of a second clock signal and having a function to correct the oscillation frequency of the second clock signal on the basis of the first clock signal, and further to a clock signal oscillation frequency adjusting method.
Still additionally, the present invention relates to an oscillation circuit apparatus capable of conducting an oscillating operation at a frequency determined in accordance with a set oscillation control condition and capable of temporarily stopping the oscillation operation.
Moreover, the present invention relates to a microcomputer including a frequency multiplication circuit for multiplying a frequency of a reference clock signal to output the frequency-multiplied reference clock signal and a CPU capable of supplying the multiplied clock signal as an operation clock signal.
Still moreover, the present invention relates to a microcomputer provided with a CPU capable of setting a low power dissipation mode to stop its operation temporarily while maintaining its internal state.
Yet moreover, the present invention relates to a memory interface circuit apparatus connected between a CPU and one or more ROMs providing a data bus width larger than that of the CPU to, when the CPU reads out data from the ROM, control the readout of the data.
2) Description of the Related Art
Japanese Patent Laid-Open Nos. HEI 6-138975, 6-75827 and 5-165543 disclose the techniques of improving the reliability at the start of oscillation by detecting a rise (leading) of a clock (stable state of the oscillation frequency) or monitoring an oscillation state of an oscillation circuit and using a watch dog timer and of making the switching to another clock signal when a clock signal stops.
In addition, Japanese Patent Laid-Open No. HEI 11-337597 discloses a microcomputer having a function to connect the frequency of a clock signal outputted from a CR oscillation circuit.
In general, in a case in which an oscillation operation of an oscillation circuit is resumed after once stopped, it takes time until its oscillation frequency reaches a set oscillation frequency. For example, FIG. 37 shows an arrangement of an analog PLL (Phase Locked Loop) circuit, generally designated at reference numeral 200. In FIG. 37, a phase comparator 201 receives a reference clock signal from a reference oscillator 202 and further receives an oscillation output signal from a VCO (voltage controlled oscillator) 203 through a programmable divider (frequency divider) 204. Moreover, the phase comparator 201 outputs a voltage signal corresponding to a phase difference therebetween through a charge pump circuit 205 to the VCO 203.
FIG. 38 is an illustration of one example of a timing chart in a case in which the oscillation operation of the PLL circuit 200 is resumed from a stopped state. In a PLL circuit, the time until its oscillation frequency reaches a target oscillation frequency owing to the operation of a phase comparator is referred to as a “lock time”, and this lock time becomes relatively long as indicated by (e) of FIG. 38.
Still additionally, Japanese Patent Laid-Open No. 2000-357947 discloses a technique of, in a DPLL circuit forming a digital controlled type PLL circuit, for shifting to a low power dissipation mode, stopping the oscillation operation of a ring oscillator of a frequency multiplication circuit. In this technique, the employment of the ring oscillator achieves the shortening of the time needed for the shifting from a low power dissipation mode to a normal mode.
In a conventional microcomputer, for switching the oscillation frequency of a clock signal or a signal source, the maximum time needed for the switching is estimated in advance and the control is resumed while waiting for this time. Accordingly, the CPU waits for the elapse of a redundant stand-by time, which leads to lowering the processing efficiency.
Yet additionally, Japanese Patent Laid-Open No. HEI 6-138975 discloses a technique of, in a microcomputer using a plurality of clock signals concurrently, issuing an interrupt request to a CPU at the timing of the completion of the rising of a clock signal for making a notification.
In a microcomputer, in the case of the occurrence of a state in which there is no need for a CPU to conduct the processing, a low power dissipation mode is taken to reduce the power dissipation in a manner such that the oscillation operation is stopped in a state where its internal state is kept (for example, Japanese Patent Laid-Open No. HEI 11-305888).
A microcomputer is designed to change a level of an external signal output terminal for controlling an external device connected to that terminal. In this case, the output level of the terminal and the term for which the terminal is made active are set according to a program.
Moreover, in particular, in a microcomputer including a battery as an operation power supply, in a case in which there is no need for a CPU to conduct the processing, the shifting to the low power dissipation mode for the reduction of the power dissipation is made by stopping the oscillation operation for a clock signal while maintaining its internal state. In this case, the internal processing in the microcomputer, the control of an external device, or the like is scheduled to be periodically implemented in a manner such that, for example, the low power dissipation mode and the normal mode are alternately taken as shown in FIG. 39.
Alternatively, in a case in which there is a need to conduct the processing irregularly in accordance with some event occurring in the exterior of the microcomputer, the event can be used as a release factor from the low power dissipation mode so that the shifting to the normal mode is made in response to the occurrence of the event for implementing the processing.
The CPU reads out instruction codes stored in a ROM and decodes the instruction codes for the implementation. Moreover, in this case, the data bus width of the CPU agrees with the number of bits. Moreover, if the CPU is of an RISC (Reduced Instruction Set Computer) type, in general the readout of the instruction codes is made according to cycle. Therefore, the operating speed of the CPU (or, the microcomputer) depends upon the data readout speed of the ROM.
However, in the case of using two clock signals concurrently, no technique based on a concept of improving the reliability on the entire operation thereof exists. For example, in a case in which a microcomputer is equipped with a watch dog timer (WDT) which operates with a clock signal independent of an operation clock signal for a CPU, it is considered to additionally monitor the operation clock signal by the WDT.
In this case, it is expectable that the WDT clearing cycle of the CPU is prolonged because the frequency of the operation clock signal lowers and the WDT immediately falls into an overflow state so that a reset takes place. However, since the intended monitoring function of the WDT is not prepared to conduct the clearing operation at a strict timing, difficulty is encountered in expecting it additionally along with a clock monitoring function.
Furthermore, for example, a CR oscillation circuit which can be constructed at a low cost is frequently employed as a clock source of the WDT. However, the CR oscillation circuit is susceptible to temperature or voltage and, hence, the monitoring time of the WDT can vary so that there is a possibility that the WDT falls into an overflow state even if the CPU makes clear the WDT according to the design, thereby causing the occurrence of a reset.
Meanwhile, the technique disclosed in Japanese Patent Laid-Open No. HEI 11-337597 makes the frequency correction step by step in a minimum unit until the frequency of a clock signal becomes equal to a set target value. This takes a long time for the correction.
Moreover, in the technique disclosed in Japanese Patent Laid-Open No. 2000-357947, cycle measurement data on a reference clock signal, which acts as a control condition for setting an oscillation frequency, is reset in response to the shifting to a low power dissipation mode and, hence, in the case of the shifting from the low power dissipation mode to the normal mode, there is a need to again measure and acquire the measurement data. For this reason, there is a problem in that the time until the oscillation frequency reaches a desired oscillation frequency is delayed by the time needed for the re-measurement.
However, so far, there has not been known a technical concept that a CPU is made to use one clock signal finally and, in a microcomputer made to carry out the switching on the clock signal, the stand-by time of the CPU associated with the clock switching is shortened to the utmost.
On the other hand, in the case of the conventional microcomputer disclosed in Japanese Patent Laid-Open No. 2000-357947, an external noise is applied thereto during the shifting to the low power dissipation mode, there is a possibility that the output level of an external output terminal varies. For example, when the microcomputer is designed to control the driving of a motor, the level of the external output terminal is controlled to stop the rotation of the motor at the shifting to the low power dissipation mode. In this state, if the output level of the external output terminal varies due to an external noise, the rotation of the motor occurs.
For example, when a program is executed in the normal mode, the program sets the level of the external output terminal (for example, High), maintains that level during the output time period, and brings the level into the original value in response to the end of the output time period (for example, Low). In addition, for the detection of the output time period, the program uses a timer made to operate on the basis of an operation clock (machine clock) or the like.
Moreover, although the program can carry out another processing concurrently during the aforesaid output time period, the processing executable concurrently do not always exist. In this case, in consequence, the CPU is activated only for maintaining the terminal output level. Still moreover, during the time period, the operation clock continues, which leads to an increase in current dissipation.
For example, in a case in which the readout speed of the ROM is low, for enhancing the processing speed of the CPU, it is considered to interleave the ROM. However, only the simple interleaving requires a wait cycle for the readout of instruction codes because the first access to the ROM depends upon the readout speed of the ROM.
For solving such problems, there has been known a method in which the instruction readout addresses of the CPU corresponding to a predetermined number of cycles are outputted in advance to reduce the wait cycle. However in this case, there is a need to construct an internal circuit of the CPU accordingly, and it is not realizable with the general-purpose CPU.